Multi-layered modules or packages are in widespread use in the semiconductor industry to mechanically support and electrically connect integrated circuit chips. Modules can be configured to mount a single chip or multiple chips, thus giving rise to the designations "SCM" for single chip modules and "MCM" for multi-chip modules.
A module supplies the chip with signals and power, and performs other functions such as heat removal, physical support and protection from the environment. Another important function is simply to redistribute the tightly packed I/Os of the chip to the I/Os of a printed wiring board.
A typical module, whether a SCM or MCM, is made of multiple layers of alternatingly arranged dielectric and conductive layers. The conductive layers are patterned, typically using photolithographic techniques, and adjacent conductive layers can be electrically connected by forming vias through the dielectric layers. These connections enable the interconnection of a chip to its package, and the package to a corresponding printed wiring board (PWB). Proper via formation is thus an important aspect of building multi-level metal systems used to make packaging.
In many chip packaging techniques, bonding pads are formed on the outer surfaces of the package over vias to facilitate chip/package/PWB connections. Bonding pads of the package must be precisely formed and accurately positioned to ensure proper electrical and mechanical connection. Moreover, where solder balls are formed on the bonding pads, such as in flip-chip packaging, properly formed bonding pads are a prerequisite to a well formed solder ball.
A known method of forming a bonding pad/solder ball connection is shown in FIG. 1. A blind via is formed by drilling a laminated substrate 10 from the outer surface-side of the substrate. The drilling step removes material from the upper-most dielectric layer 12 to form a slightly tapered recess. Next, the recess is plated with conductive material using any of the deposition techniques that are well known in the microelectronic fabrication art. The plated recess is then filled with a conductive filler material 14.
The filler material must be leveled to be coplanar with the outer surface of the outer conductive layer 16. A solder ball 18, formed on the conductive layer 16, is then used to connect the substrate 10 to an integrated circuit chip 20. The area under the solder ball 16 is patterned to form a bonding pad.
While the above process makes an adequate connection, it is relatively difficult and costly to level the filler in the blind via to make it co-planar with the conductive layer 16. If the blind via is not completely filled, contaminants can become entrapped causing problems in later soldering operations.
Another technique for forming circuit interconnects, illustrated in FIG. 2, involves forming through vias 22 in a laminated substrate 24, plating the vias, and then forming via capture pads 26 on top of the vias 22. Separate chip attach capture pads 28 are connected to respective ones of the via capture pads 26. The chip attach capture pads 28 provide an area to attach the chip solder balls (not shown). In this arrangement, the via capture pads are covered by a solder mask (not shown) to prevent solder from flowing down the through vias 22.
Although the separate capture pads 26 are commonly used, they take up a large amount of space, thus limiting the ability to route signal lines between the pads, as shown by the broken-line directional arrows "A" and "B" of FIG. 2. These arrows represent restricted routing channels and thus a limitation on the wiring density of the package.